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TLDR
OpenAI and Synopsys are developing GPT-Synopsys, an AI agent that iteratively modifies chip designs, runs engineering tools, and interprets results to meet timing, power, and correctness requirements. The tool is still in development with early customer engagements, and its predecessor, the Jalapeno inference accelerator, reached tape-out in 9 months with AI assistance but not necessarily from GPT-Synopsys. The real story is that AI is being applied to the entire chip design workflow, not just isolated tasks, but the impact on engineering time remains unquantified.
Key points
OpenAI and Synopsys announced a development agreement for GPT-Synopsys on September 30th, 2026.
GPT-Synopsys is an AI agent that makes design changes, runs engineering tools, and interprets results.
Jalapeno, OpenAI's first custom inference accelerator, was announced in June and developed with Broadcom.
OpenAI reports Jalapeno went from initial design to manufacturing tape-out in 9 months.
GPT-Synopsys is still in development with no general availability date announced.
Tools mentioned
Techniques
- iterative design optimization
- AI-assisted chip design verification
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Transcript (captions)
This signal arrives too late, so the circuit misses its speed target. It's an illustrative design, but the trade-off is real. Can we make it faster without pushing power use too high? Enlarge that
cell and the signal can arrive sooner, but power use rises and the cell takes more space. The power budget wasn't impressed. So, what happens when AI helps design the hardware that will run
future AI? The proposed job is to make changes like this, run engineering tools, and interpret what comes back. If power use comes back too high, the agent revises the design and runs the tools
again. Making the circuit faster doesn't mean it's met all its requirements. Each check answers a different question. Does the change circuit still produce the same outputs for the same inputs? Does
it meet timing requirements? How much power is it estimated to consume? A convincing explanation can't answer those questions. The tools have to check the design and engineers review the
results. That's the workflow OpenAI and Synopsis want GPT Synopsis to operate. They announced the development agreement on September 30th, 2026. Early customer engagements are underway. The model
still in development and they haven't announced a general availability date. There's an earlier chip in this story. Jalapeno announced in June as OpenAI's first custom inference accelerator. It's
hardware for running AI models developed with Broadcom. Open AAI designed its architecture. Broadcom contributed implementation and networking. The companies say open AI models helped with
parts of design and optimization. That doesn't establish that GPT synopsis was involved. They report 9 months from initial design to manufacturing tape out. That's the design handoff for
manufacturing, not broad deployment. And it doesn't tell us how much time AI alone saved. By August, OpenAI reported working silicon with measured results. The proposed next step is a specialized
model that operates more of the chip design workflow we've just followed. For chip engineers, I judge this by the check design and the review workload. Can it deliver better verified designs
with less engineering time?